Series 115 (Lot 15051)

This portfolio is generally related to distributed computing system having reconfigurable system clock to alleviate delays in processing data so that memory access bottlenecks are not compounded within distributed computing systems. Also disclosed is an external communications interface which communicates with a second computing node by clocking data into or out of the first computing node using the first clock signal. The system determines the second frequency of the second clock signal to generate a substitute clock signal operating at the second frequency and communicate with the computing device using the substitute clock signal. The technology may be implemented in distributed computing system, inter-die communication system, firmware applications, data centres, etc.

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