IP3 2024 – Semiconductor Packaging (Lot 11712)

This patent is generally related to an electronic device. Techniques are disclosed to manufacture an electronic device having a two-dimensional semiconductor and techniques to reduce a contact resistance between a two-dimensional semiconductor layer and an electrode. Disclosed is an electronic device using a two-dimensional semiconductor having a two-dimensional semiconductor layer doped into n-type or p-type. Also disclosed is a first electrode formed on a first area of the two-dimensional semiconductor layer and a second electrode formed on a second area of the two-dimensional semiconductor layer and spaced from the first electrode. Further disclosed are techniques to form pattern in the first area and the second area, and the first electrode and the second electrode are formed on areas corresponding to the patterns. The technology may be implemented in electronic devices, solar energy systems, Magnetic NEMS, etc.

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