IP3 2023 – Semiconductor Packaging 2 (LOT 14664)

This lot is generally related to fabrication and bonding of wafers for integrated circuit (IC) devices for compensating nonplanarities in wafer surfaces. Disclosed is a technique of wafer bonding by providing a first bonding site on a surface of a first wafer and depositing a first bonding stack on a surface of a second wafer. Also disclosed are techniques to form a groove in the surface of the first wafer and aligning and mating so that the first bonding stack on the second wafer contacts the first bonding site on the first wafer so that the first groove lies entirely within the first bonding site. Further disclosed are techniques to heat the first and second wafers to reflow the first bonding stack on the second wafer to form the bonding structure. The technology may be implemented in integrated circuits (ICs), fabricating semiconductor chips, etc.