IP3 2023 – Semiconductor Manufacturing 3 (LOT 12655)

This lot is generally related to fabrication of an off nitride power semiconductor device. Techniques are disclosed to manufacture low cost, efficient off nitride power semiconductor device driving circuit by removing two-dimensional electron gas. Disclosed is a fabrication technique of a normally off nitride semiconductor device by forming a buffer layer on a substrate, form a first nitride semiconductor layer on the buffer layer and pattern a source region by masking a barrier made of SiO2 in a gate region. Also disclosed are techniques to form a hetero-junction layer below the source region by forming a second nitride semiconductor layer with a band gap and remove the masking layer. Further disclosed are techniques to form an insulating film on the second nitride semiconductor layer and a layer where the masking barrier is removed. The technology may be implemented in FETs, integrated circuits (ICs), digital on-off switches, etc.

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