IP3 2023 – Semiconductor Manufacturing 2 (LOT 14779)

This lot is generally related to a reconfigurable logic-in memory device to balance processing speed between a processor and a memory when processing large amounts of data. Disclosed is a reconfigurable logic-in-memory device utilizing a CMOS and silicon transistors with a drain region, a first channel region, a second channel region, a source region, and a gate region. The silicon transistor performs a first channel operation to form a first positive feedback loop and the second channel region depending on a level of a gate voltage applied through the gate region or performs a second channel operation while forming a second positive feedback loop depending on the level of a gate voltage applied through the gate region. The logic-in-memory device may provide different logic gate functions based on a first channel operation state or a second channel operation state. The technology may be implemented in semiconductor devices, reconfigurable logic-in-memory devices, etc.

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