IP3 2023 – Communication Circuits (LOT 14772)

This lot discloses a sub-sampling phase-locked loop (SSPLL) used in an oscillator to reduce jitter of the clock and reduces noise to and the power consumption. Disclosed is a sub-sampling phase locked-loop having a first phase output unit for sub-sampling an output clock of a digitally controlled oscillator and generating a sign bit related to a voltage-domain phase. The system has a second phase output unit for outputting a gain bit related to a time-domain phase based on a pulse width set and a threshold time set according to a reference clock. Also disclosed is a digital loop filter for calculating a digital loop filter value based on the sign bit and the gain bit for controlling a phase of the output clock. The technology may be implemented in analog-to-digital (AD) converters, oscillators, etc.