IP3 2022 – Semiconductor Packaging (LOT 13579)

This lot is generally related to a technique to repair a three-dimensional semiconductor circuit. Disclosed is a technique to fabricate a stacked semiconductor device by integrating multiple semiconductor platforms having multiple IC chips. The integrated subsurface is interconnected using an input/output plug or high-performance cables. All semiconductor elements are interconnected using a flip chip connector which allows replacement of any defective element. The technology may be implemented in substrates, circuits, connectors, ICs, PCBs, testers, heat sinks, cooling systems, etc.

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