IP3 2020-Memory Circuits (LOT 11607)

This lot is generally related to memory.  Disclosed are memory devices used in multiple processor computers/devices which can simultaneously process multiple access requests without compromising on access speed and system performance and various techniques to control memory to reduce wait time and maximize bandwidth utilization.  The memory devices for multiple processor computers/devices use a command-and-control signal port, an address port, a data port with multiple simultaneous data channels, a mode register and multiple memory banks divided into sub banks.  Also disclosed are techniques to control memory, which read multiple memory access requests from a buffer, determine whether a first bank buffer is not full and transfer next access request to the buffer.  If the buffer is full, then check whether the second bank buffer is not full and transfer the request to the second buffer.  These techniques also store buffer information which has each request to transfer commands of the bank controller to the memory.  The technology may be implemented in memory devices, memory controllers, read/write circuits, memory circuits, computers, smart phones, laptops, PDAs, tablets and other processor-based devices.