Acquired Portfolios

Methods for Avoiding Livelock in Multi-Core Systems

Speculative Cache Tag Evaluation

Mechanism for Solving a Writeback Race in CMP Systems

Efficient, Scalable and High Performance Mechanism for Handling IO Requests

Efficient Mechanism for Correlating PDTrace Streams Between at Least One Processor and a Coherence Manager

Mechanism for Maintaining Consistency of Data Written by IO Devices

Coherence Manager Trace Formats

Support for Multiple Coherence Domains

String Copy Instruction and System to Implement the Same

Apparatus and Method for Hardware Initiation of Emulated Instructions

Apparatus and Method for Accelerated Hardware Page Table Walk

Programmable Memory Address Segments

Interrupt and Exception Handling for Multi-Streaming Digital Processors

Wire-speed Multi-Dimensional Packet Classifier

Fetch and Dispatch Decoupling Mechanism for Multi-Streaming Processors

Variable Page Size Translation Lookaside Buffer

Load Latency of Zero for Floating Point Load Instructions Using a Load Data Queue

Memory Translation

Address Queue

Redundant Mapping Tables

System and method for automatic hardware interrupt handling

Data cache way prediction

Coherent instruction cache utilizing cache-op execution resources

Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof

Substituting portion of template instruction parameter with selected virtual instruction parameter

Interrupt and exception handling for multi-streaming digital processors

Horizontally-shared cache victims in multiple core processors

Microprocessor system for virtual machine execution

Merged floating point operation using a modebit

Preemptive multitasking employing software emulation of directed exceptions in a multithreading processor

Data transfer bus communication to receive data by sending request instruction attached with identifier indicating processor and thread context identities

Carry look-ahead adder with generate bits and propagate bits used for column sums

Apparatus and method for guest and root register sharing in a virtual machine

Data cache virtual hint way prediction, and applications thereof

Virtual machine coprocessor for accelerating software execution

System and method for improving memory transfer

Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions

Variable register and immediate field encoding in an instruction set architecture

Pushbutton remote control

A Stream Processing Unit for a Multi-Streaming Processor

Mechanism for Programmable Modification of Memory Mapping Granularity

Method and Apparatus for Optimizing Selection of Available Contexts for Packet Processing in Multi-Stream Packet Processing

Method and Apparatus for Allocating and De-allocating Consecutive Blocks of Memory in Background Management

Method and Apparatus for Non-Speculative Pre-Fetch Operation in Data Packet Processing

Extended Instruction Set for a Packet Processing Applications

Method and Apparatus for Clearing Hazards Using Jump Instructions

A Method for Providing High Frequency Scan Testability on Low Speed Testers

Processor Including Thread Scheduler Based on Instruction Stall Likelihood Prediction

Process Core and Method for Managing Branch Misprediction in an Out-of-Order Processor Pipeline

Processor Having a Data Mover Engine that Associates Register Addresses with Memory Addresses

Processor Utilizing a Loop Buffer to Reduce Power Consumption

Microprocessor Having a Power-Saving Instruction Cache Way Predictor and Instruction Replacement Scheme

Efficient Resource Arbitration

Distributive Scoreboard Scheduling in an Out-of-Order Microprocessor

Software and Techniques for Generation of Self-Checking Random Programs

Low-Overhead/Power-Saving Processor Synchronization Mechanism, and Applications Thereof

Micro Tag Array to Preserve Data Cache Access Power

Twice Issued Conditional Move Instruction, and Applications Thereof

Load/Store Unit for a Processor, and Applications Thereof

Data Cache Virtual Hint Based Way Prediction, and Applications Thereof

Apparatus and Method for Tracing Instructions with Simplified Instruction State Descriptors

Method for Reducing Handling of Write Data

Apparatus, method and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Software programmable hardware state machines

Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency

Method and apparatus for clearing hazards using jump instructions

Method and apparatus for binding shadow registers to vectored interrupts

Apparatus and method for profiling software performance on a processor with non-unique virtual addresses

External trace synchronization via periodic sampling

Random cache line refill

Instruction encoding for system register bit set and clear

System and method for extracting fields from packets having fields spread over more than one register

Processor core and multiplier that support a multiply and difference operation by inverting sign bits in booth recoding

Apparatus and method for condensing trace information in a multi-processor system

Processor core and multiplier that support both vector and single value multiplication

Apparatus and method for controlling the exclusivity mode of a level-two cache

Microprocessor with dual-level address translation

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Automated digital circuit design tool that reduces or eliminates adverse timing constraints do to an inherent clock signal skew, and applications thereof

Systems and methods for controlling the use of processing algorithms, and applications thereof

Data cache receive flop bypass

Apparatus and method for controlling the exclusivity mode of a level-two cache

Automated digital circuit design tool that reduces or eliminates adverse timing constraints due to an inherent clock signal skew, and applications thereof

Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

Method and apparatus for binding shadow registers to vectored interrupts

Interrupt and exception handling for multi-streaming digital processors

Bifurcated transaction selector supporting dynamic priorities in multi-port switch

Apparatus and method for forming a mixed signal circuit with fully customizable analog cells and programmable interconnect

Transaction selector employing transaction queue group priorities in multi-port switch

Efficient, scalable and high performance mechanism for handling IO requests

Processor with improved accuracy for multiply-add operations

Virtual processor based security for on-chip memory, and applications thereof

Coprocessor load data queue for interfacing an out-of-order execution unit with an in-order coprocessor

Method and apparatus for global ordering to insure latency independent coherence

Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof

Power management for system having one or more integrated circuits

Providing extended precision in SIMD vector arithmetic operations

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

Microprocessor with improved data stream prefetching

Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states

Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated

Context sharing between a streaming processing unit (SPU) and a packet management unit (PMU) in a packet processing environment

System and method for managing the design and configuration of an integrated circuit semiconductor design

Support for multiple coherence domains

Apparatus and method for processing template based user defined instructions

Dynamic selection of a compression algorithm for trace data

Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch

Horizontally-shared cache victims in multiple core processors

Protecting trade secrets during the design and configuration of an integrated circuit semiconductor design

Alignment and ordering of vector elements for single instruction multiple data processing

Microprocessor with improved data stream prefetching using multiple transaction look-aside buffers (TLBs)

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Speculative cache tag evaluation

Software emulation of directed exceptions in a multithreading processor

Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions

Extended precision accumulator

Efficient resource arbitration

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion

Processor utilizing a loop buffer to reduce power consumption

Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory

Configurable co-processor interface

System debug and trace system and method, and applications thereof

Method for extracting fields from packets having fields spread over more than one register

Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme

Interrupt and exception handling for multi-streaming digital processors

Interface with credit-based flow control and sustained bus signals

Trace control from hardware and software

System for synchronizing an in-order co-processor with an out-of-order processor using a co-processor interface store data queue

Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing

Micro tag array having way selection bits for reducing data cache access power

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Methods for reducing data cache access power in a processor using way selection bits

Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor

Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency

Multithreading instruction scheduler employing thread group priorities

Methods and apparatus for managing a buffer of events in the background

Microprocessor with improved data stream prefetching

Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages

System, method, and computer program product for conditionally suspending issuing instructions of a thread

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Multithreading instruction scheduler employing thread group priorities

Mechanisms for dynamic configuration of virtual processor resources

Configurable co-processor interface

Apparatus and method for tracing processor state from multiple clock domains

Multi-ISA instruction fetch unit for a processor, and applications thereof

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

Microprocessor instructions for performing polynomial arithmetic operations

Mapping system and method for instruction set processing

Synchronized storage providing multiple synchronization semantics

Processor core and method for managing branch misprediction in an out-of-order processor pipeline

Queueing system for processors in packet routing operations

System and method for propagating operand availability prediction bits with instructions through a pipeline in an out-of-order processor

Conditional branch execution in a processor having a data mover engine that associates register addresses with memory addresses

Conditional branch execution in a processor having a read-tie instruction and a data mover engine that associates register addresses with memory addresses

Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses

Multithreaded dynamic voltage-frequency scaling microprocessor

Processor having a compare extension of an instruction set architecture

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Processor core and method for managing program counter redirection in an out-of-order processor pipeline

Avoiding livelock using a cache manager in multiple core processors

Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack

Method for latest producer tracking in an out-of-order processor, and applications thereof

Virtual machine coprocessor facilitating dynamic compilation

Leaky-bucket thread scheduler in a multithreading microprocessor

Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch

Interstream control and communications for multi-streaming digital processors

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

Preventing writeback race in multiple core processors

Avoiding livelock using intervention messages in multiple core processors

HyperJTAG system including debug probe, on-chip instrumentation, and protocol

Microprocessor with improved data stream prefetching

Method and apparatus for binding shadow registers to vectored interrupts

Method and apparatus for binding shadow registers to vectored interrupts

Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor

Processor accessing a scratch pad on-demand to reduce power consumption

Background memory manager that determines if data structures fits in memory with memory state transactions map

Microprocessor with improved data stream prefetching

Return data selector employing barrel-incrementer-based round-robin apparatus

Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor

Apparatus and method for discovering a scratch pad memory configuration

Microprocessor with improved data stream prefetching

Selection of ISA decoding mode for plural instruction sets based upon instruction address

Microprocessor with improved data stream prefetching

Method and apparatus for improved computer load and store operations

Context switching processor with multiple context control register sets including write address register identifying destination register for waiting context to store returned data from external source

Microprocessor with improved data stream prefetching

Full scan solution for latched-based design

Providing extended precision in SIMD vector arithmetic operations

Queueing system for processors in packet routing operations

Configurable prioritization of core generated interrupts

Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor

Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme

System and method for extracting fields from packets having fields spread over more than one register

Data cache virtual hint way prediction, and applications thereof

Smart memory based synchronization controller for a multi-threaded multiprocessor SoC

Binary polynomial multiplier

Instruction encoding for system register bit set and clear

Apparatus and method for software specified power management performance using low power virtual threads

Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler

Hyperjtag system including debug probe, on-chip instrumentation, and protocol

Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution

Method and apparatus for masking a microprocessor execution signature

Apparatus and method for automatic low power mode invocation in a multi-threaded processor

Apparatus and method for discrete test access control of multiple cores

Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor

Method and apparatus for redirection of operations between interfaces

Instruction encoding for system register bit set and clear

Fetch and dispatch disassociation apparatus for multistreaming processors

Method and apparatus for global ordering to insure latency independent coherence

Functional validation of a packet management unit

Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration

Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts

Tracing out-of order load data

Microprocessor with improved data stream prefetching

Trace control based on a characteristic of a processor’s operating state

Extended-precision accumulation of multiplier output

Read-only access to CPO registers

User controlled trace records

Atomic update of CPO state

Trace control from hardware and software

Microprocessor with improved data stream prefetching

Configurable co-processor interface

Method for allocating memory space for limited packet head and/or tail growth

Alignment and ordering of vector elements for single instruction multiple data processing

Extended precision accumulator

Distributed tap controller

Configurable out-of-order data transfer in a coprocessor interface

Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams

Partial bitwise permutations

Processor having a compare extension of an instruction set architecture

Full scan solution for latched-based design

Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors

Method and apparatus for non-speculative pre-fetch operation in data packet processing

Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset

Configurable co-processor interface

Random cache line refill

Microprocessor instructions for efficient bit stream extractions

Random slip generator

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Processor with improved accuracy for multiply-add operations

Method for latest producer tracking in an out-of-order processor, and applications thereof

Mechanisms for assuring quality of service for programs executing on a multithreaded processor

Prefetching hints

High performance RISC instruction set digital signal processor having circular buffer and looping controls

Fetch and dispatch disassociation apparatus for multi-streaming processors

Trace control from hardware and software

Method and apparatus for predicting characteristics of incoming data packets to enable speculative processing to reduce processor latency

Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts

Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor

Interrupt and exception handling for multi-streaming digital processors

Coherent data apparatus for an on-chip split transaction system bus

Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel execution

Floating-point processor with improved intermediate result handling

Processor having an arithmetic extension of an instruction set architecture

Programmable page table access

Low latency system bus interface for multi-master processing environments

Processor having a conditional branch extension of an instruction set architecture

System, method and computer program product for web-based integrated circuit design

Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions

Interstream control and communications for multi-streaming digital processors

Instruction specified register value saving in allocated caller stack or not yet allocated callee stack

Apparatus and method for discovering a scratch pad memory configuration

Apparatus and method for relative position annotation of standard cell components to facilitate datapath design

System and method for improving the accuracy of reciprocal square root operations performed by a floating-point unit

Method and apparatus for redirection of operations between interfaces

Method and apparatus for disassociating power consumed within a processing system with instructions it is executing

Apparatus and method for generating multi-phase signals with digitally controlled trim capacitors

Floating-point processor with operating mode having improved accuracy and high performance

Method and apparatus for clearing hazards using jump instructions

Mechanism for proxy management of multiprocessor storage hierarchies

Mechanism for proxy management of multiprocessor virtual memory

Interrupt and exception handling for multi-streaming digital processors

Methods and apparatus for managing a buffer of events in the background

Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors

Clustering stream and/or instruction queues for multi-streaming processors

System and method for extracting fields from packets having fields spread over more than one register

Method and apparatus for non-speculative pre-fetch operation in data packet processing

Wire-speed multi-dimensional packet classifier

Optimized external trace formats

Trace control block implementation and method

Queueing system for processors in packet routing operations

Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing

Method for allocating memory space for limited packet head and/or tail growth

System and method for speeding up EJTAG block data transfers

Dynamic selection of a compression algorithm for trace data

Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management

Functional validation of a packet management unit

System and method of controlling software decompression through exceptions

Program counter and data tracing from a multi-issue processor

Prefetching hints

External trace synchronization via periodic sampling

Fetch and dispatch disassociation apparatus for multistreaming processors

Extended instruction set for packet processing applications

Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values

Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory

Method for providing extended precision in SIMD vector arithmetic operations

System and method to trace high performance multi-issue processors

Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch

Horizontally-Shared Cache Victims in Multiple Core Processors

Data Cache Virtual Hint Way Prediction, and Applications Thereof

Twice Issued Conditional Move Instruction, and Applications Thereof

Instruction prediction based on filtering

Coherent Instruction Cache Utilizing Cache-Op Execution Resources

Compact Instruction Set Architecture

System and Method for Improving Memory Transfer

Power Reduction Instruction Cache in a Multi-Thread Processor Core

MIPS32 Enhanced VA Scheme

Achieving Glitch-Free Clock Domain Crossing Signals Using Formal Verification, Static Timing Analysis, and Sequential Equivalence Checking

Output synchronization-free, high-fanin dynamic NOR gate

Address queue

Prefetching hints

Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructions

Translation lookaside buffer with virtual address conflict prevention

Alignment and ordering of vector elements for single instruction multiple data processing

Register transfer unit for electronic processor

Register file access

Interstream control and communications for multi-streaming digital processors

Burst-configurable data bus

Instruction prediction based on filtering

Scratchpad RAM memory accessible in parallel to a primary cache

Method and apparatus for tracking and update of LRU algorithm using vectors

Output synchronization-free, high-fanin dynamic NOR gate

Prioritized instruction scheduling for multi-streaming processors

Locked read/write on separate address/data bus using write barrier

Scalable on-chip system bus

Mechanism for programmable modification of memory mapping granularity

Cache memory with dual-way arrays and multiplexed parallel output

Data release to reduce latency in on-chip system bus

System for prediction and control of power consumption in digital system

Method and apparatus for predicting floating-point exceptions

Mechanism to extend computer memory protection schemes

Mechanism for extending properties of virtual memory pages by a TLB

Register set extension for compressed instruction set

Queuing System for Processors in Packet Routing Operations

Random Slip Generator

Random Cache Line Refill Order

An Improved and Extended Family of Network Services Processors

Cache Scrambling Interface

Virtual Machine Coprocessor for Accelerating Software Execution

Latency Independent Coherence Protocol

Latency Independent Coherence Protocol

Virtual Machine Coprocessor for Accelerating Software Execution

Mechanism for Assuring Quality of Service for Programs Executing on a Multithread Processor

Mechanism for Assuring Quality of Service for Programs Executing on a Multithread Processor

Mechanism for Assuring Quality of Service for Programs Executing on a Multithread Processor

HYPERJTAG: Protocol and Design Providing Multiple Independent JTAG Debug Probe Connections to Multiple Processor Cores on One Integrated Circuit Through One Set of Signals

Interrupt reporting for single-bit memory errors

System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory

Slot determination mechanism using pulse counting

Two-level translation look-aside buffer using partial addresses for enhanced speed

Translation lookaside buffer shutdown scheme

Variable page size per entry translation look-aside buffer

Low-noise high-speed output buffer and method for controlling same

Sense amp for bit line sensing and data latching

Redundant element substitution apparatus

Two-level cache memory system

Binary shifter

Clock distribution system for an integrated circuit device

Translation lookaside buffer shutdown scheme

Redundancy selection apparatus and method for an array

System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders

System and Method for booting computer for operation in either of two byte-order modes

Backward-compatible computer architecture with extended word size and address space

Unified floating point and integer datapath for a RISC processor

Hybrid cache having physical-cache and virtual-cache characteristics and method for accessing same

Apparatus for detecting any single bit error, detecting any two bit error, and detecting any three or four bit error in a group of four bits for a 25-or 64-bit data word

Mechanism and method for integer divide involving pre-alignment of the divisor relative to the dividend

Compact dual function adder

Memory system including local and global caches for storing floating point and integer data

System for booting computer for operation in either one of two byte-order modes

Variable page size translation lookaside buffer

Debug mode for a superscalar RISC processor

Cache memory system employing virtual address primary instruction and data caches and physical address secondary cache

Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction

RISC processor having improved instruction fetching capability and utilizing address bit predecoding for a segmented cache memory

Backward-compatible computer architecture with extended word size and address space

System and method for controlling split-level caches in a multi-processor system including data loss and deadlock prevention schemes

System and method for obtaining correct byte addresses by using logical operations on 2 least significant bits of byte address to facilitate compatibility between computer architectures having different memory orders

TLB with two physical pages per virtual tag

Method and apparatus for retarting pipeline processing

Apparatus for processing instructions in a computing system

Precise translation lookaside buffer error detection and shutdown circuit

Method for preventing multi-level cache system deadlock in a multi-processor system

Low-power, compact digital logic topology that facilitates large fan-in and high-speed circuit performance

Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline

Software invalidation in a multiple level, multiple cache system

Consistently specifying way destinations through prefetching hints

Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns

Conflict resolution in interleaved memory systems with multiple parallel accesses

Pipeline processor with enhanced method and apparatus for restoring register-renaming information in the event of a branch misprediction

Method for providing extended precision in SIMD vector arithmetic operations

System and method for fetching multiple groups of instructions from an instruction cache in a RISC processor system for execution during separate cycles

Alignment and ordering of vector elements for single instruction multiple data processing

Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address

Processor chip for using an external clock to generate an internal clock and for using data transmit patterns in combination with the internal clock to control transmission of data words to an external memory

High Performance System Bus Interface

Method and Apparatus for Improved Computer Load and Store Operations

Wire-speed Multi-Dimensional Packet Classifier

Detection and prevention of write-after-write hazards, and applications thereof

Load/store unit for a processor, and applications thereof

APPARATUS AND METHOD FOR TRACING INSTRUCTIONS WITH SIMPLIFIED INSTRUCTION STATE DESCRIPTORS

APPARATUS AND METHOD FOR FORMING A BUS TRANSACTION TRACE STREAM WITH SIMPLIFIED BUS TRANSACTION DESCRIPTORS

Synthesized assertions in a self-correcting processor and applications thereof

System, Method and Software Application for the Generation of Verification Programs

Remote Interface for Managing the Design and Configuration of an Integrated Circuit Semiconductor Design

Reduced Handling of Writeback Data

APPARATUS AND METHOD FOR EVALUATING A FREE-RUNNING TRACE STREAM

Low-overhead/power-saving processor synchronization mechanism, and applications thereof

SEMICONDUCTOR WITH HARDWARE LOCKED INTELLECTUAL PROPERTY AND RELATED METHODS

SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR

Processor Accessing A Scratch Pad On-Demand To Reduce Power Consumption

Method and Apparatus for Improved Computer Load and Store Operations

MECHANISM FOR MAINTAINING CONSISTENCY OF DATA WRITTEN BY IO DEVICES

APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION

Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor

Apparatus For Storing Instructions In A Multithreading Microprocessor

Microprocessor with Compact Instruction Set Architecture

Methods, Systems, and Computer Program Products for Evaluating Electrical Circuits From Information Stored in Simulation Dump Files

Processor Core and Method for Managing Program Counter Redirection in an Out-of-Order Processor Pipeline

Microprocessor with Compact Instruction Set Architecture

Alignment and Ordering of Vector Elements for Single Instruction Multiple Data Processing

Method and Apparatus for Predicting Characteristics of Incoming Data Packets to Enable Speculative Processing to Reduce Processor Latency

SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES

Multithreaded Operation of A Microprocessor Cache

Apparatus and Method for Hardware Initiation of Emulated Instructions

Programmable Memory Address

Apparatus and Method for Accelerated Hardware Page Table Walk

Support for Multiple Coherence Domains

Apparatus and Method for Low Overhead Correlation of Multi-Processor Trace Information

Vector Size Agnostic Single Instruction Multiple Data (SIMD) Processor Architecture

System For Compression Of Fixed Width Values In A Processor Hardware Trace

Shared Register Pool For A Multithreaded Microprocessor

Write buffer

Risc computer with unaligned reference handling and method for the same

Method and apparatus for precise floating point exceptions

Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories

Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders

Processor controlled interface with instruction streaming

Differential bus with specified default value

Variable delay line phase-locked loop circuit synchronization system

Redundant Mapping Tables

Memory Translation

Address Queue

Memory Translation

Processor Chip Having On-Chip Circuitry for Generating a Programmable External Clock Signal & for Controlling Data.

Cache Coherency Mechanism for Multiprocessor System

Method & Apparatus For Byte Order Switching in a Computer

Load Latency of Zero for Floating Point Load Instructions Using a Load Data Queue

Apparatus for Processing Instructions in a Computing System

Redundant Mapping Tables

System Having an Address Generating Unit & a Log Comparator Packaged as an Integrated Circuit Separate from Cache Log

Instruction Prediction Based on Filtering

Prefetching Hints

Processor Having a Compare Extension of an Instruction Set Architecture

Processor Having an Arithmetic Extension of an Instruction Set Architecture

Processor Having a Conditional Branch Extension of an Instruction Set Architecture

System and Method for Improving the Accuracy of Reciprocal and Reciprocal Square Root Operations Performed by a Floating Point Unit

Processor Having an Arithmetic Extension of an Instruction Set Architecture

Processor Having a Conditional Branch Extension of an Instruction Set Architecture

Floating-Point Processor with Improved Intermediate Result Handling

Processor Having a Compare Extension of an Instruction Set Architecture

Processor Chip Having On-Chip Circuitry for Generating a Programmable External Clock Signal & for Controlling Data.

Method and Apparatus for Improved Computer Load and Store Operations

Translation Lookaside Buffer for Selection of ISA Mode

A Co-processor Interface that Enables Coprocessor-Specific Branching

Partial Bitwise Permutations

Cache Scrambling Interface

Full Scan Solution for Latched-Based Design

Virtual Machine Coprocessor for Accelerating Software Execution

Virtual Machine Coprocessor for Accelerating Software Execution

System and Method for Simulating a Multi-Stage Microprocessor

Providing Extended Precision in SIMD Vector Arithmetic Operations

Multithreading Instruction Scheduler Employing Thread Group Priorities

Multithreading Instruction Scheduler Employing Thread Group Priorities

Floating-Point Processor with Operating Mode Having Improved Accuracy and High Performance

Stream processing unit for a multi-streaming processor

System and method for improving the accuracy of reciprocal operations performed by a floating-point unit

High-frequency scan testability with low-speed testers

Integrated mechanism for suspension and deallocation of computational threads of execution in a processor

Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer

EXTENDED INSTRUCTION SET FOR PACKET PROCESSING APPLICATIONS

APPARATUS AND METHOD TO TRACE HIGH PERFORMANCE MULTI-ISSUE PROCESSORS

Compact linked-list-based multi-threaded instruction graduation buffer

High-performance RISC-DSP

Latest producer tracking in an out-of-order processor, and applications thereof

Debug Mode for a Superscalar RISC Processor

Variable Delay Line Phase-Locked Loop Circuit

Apparatus for Processing Instructions in a Computing System

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

A Method for Providing High Frequency Scan Testability on Low Speed Testers

Two Step Kill Mechanism Upon Branch Mispredict Resolution in OOO Pipeline

Microprocessor Instruction Using Address Index Values to Enable Access of a Virtual Buffer in Circular Fashion

Bifurcated Instruction Dispatch Scheduler in a Multi-Threading Microprocessor

Method of and apparatus using floating point exception signals for controlling several processors

Method & Apparatus For Byte Order Switching in a Computer

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Translation Lookaside Buffer Shutdown Scheme

Variable Delay Line Phase-Locked Loop Circuit

Optimized Pipeline Operations for Reduced Instruction Set Computers

Bus Arbitration Mechanism

Two-Level Cache Memory System

Variable Delay Line Phase-Locked Loop Circuit

Method & Apparatus For Byte Order Switching in a Computer

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Method & Apparatus for Retarting Pipeline Processing

Hybrid Cache Having Physical-Cache & Virtual-Cache Characteristics & Method for Accessing Same

Processor Chip Having On-Chip Circuitry for Generating a Programmable External Clock Signal & for Controlling Data.

Cache Coherency Mechanism for Multiprocessor System

Bus Arbitration Mechanism

Method & Apparatus for Reducing Delays Following the Execution of a Branch Instruction in an Instruction Pipeline

Self-Locating Heat Sink & Electro Magnetic Shield Assembly

Self-Locating Heat Sink & Electro Magnetic Shield Assembly

Optimized Pipeline Operations for Reduced Instruction Set Computers

RISC Processor Having Improved Instruction Fetching Capability & Utilizing Address Bit Precoding for a Segmented Cache Memory

System Having an Address Generating Unit & a Log Comparator Packaged as an Integrated Circuit Separate from Cache Log

Load Latency of Zero for Floating Point Load Instructions Using a Load Data Queue

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Conflict Resolution in Interleaved Memory Systems with Multiple Parallel Accesses

Self-Locating Heat Sink & Electro Magnetic Shield Assembly

Method & Apparatus for Retarting Pipeline Processing

Indexing & Multiplexing of Interleaved Cache Memory Arrays

Apparatus for Processing Instructions in a Computing System

Debug Mode for a Superscalar RISC Processor

RISC Computer with Unaligned Reference Handling and Method for the Same

Method of and apparatus using floating point exception signals for controlling several processors

System and Method for Booting Computer for Operation in Either of Two Byte-Order Modes

Two-Level Translation Look-Aside Buffer Using Partial Addresses for Enhanced Speed

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Method & Apparatus For Byte Order Switching in a Computer

Variable Page Size Per Entry Translation Look Aside Buffer

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Method and Apparatus for Improved Computer Load and Store Operations

Queuing System for Processors in Packet Routing Operations

Partial Bitwise Permutations

Prioritized Instruction Scheduling for Multi-Streaming Processors

Interstream Control and Communications for Multi-Streaming Digital Processors

Register Transfer Unit for Electronic Processor

Method and Apparatus for Clearing Hazards Using Jump Instructions

Mechanism to Extend Computer Memory Protection Schemes

Processor with Improved Accuracy for Multiply-Add Operations

Mechanisms for Dynamic Configuration of Virtual Processor Resources

Instruction for Initiation of Concurrent Instruction Streams in a Multithreading Microprocessor

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors

Instruction Prediction Based on Filtering

Indexing & Multiplexing of Interleaved Cache Memory Arrays

Apparatus for Processing Instructions in a Computing System

Unified Floating Point and Integer Datapath for a RISC Processor

Bifurcated Thread Scheduler in a Multithreading Microprocessor

Apparatus and Method for Automatic Low Power Mode Invocation in a Multi-Threaded Processor

RISC Computer with Unaligned Reference Handling and Method for the Same

Processor Controlled Interface with Instruction Streaming

Debug Mode for a Superscalar RISC Processor

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

System and Method for Coherency in a Split-Level Data Cache System

Variable Delay Line Phase-Locked Loop Circuit

Apparatus for Processing Instructions in a Computing System

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Instruction Prediction Based on Filtering

Translation Lookaside Buffer Shutdown Scheme

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Method of and apparatus using floating point exception signals for controlling several processors

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Translation Lookaside Buffer Shutdown Scheme

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Instruction Prediction Based on Filtering

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

System and Method for Coherency in a Split-Level Data Cache System

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

System and Method for Coherency in a Split-Level Data Cache System

A SYSTEM, METHOD AND SOFTWARE APPLICATION FOR THE GENERATION OF VERIFICATION PROGRAMS

Extended Precision Accumulator

Polynomial Arithmetic Operations

Register Transfer Unit for Electronic Processor

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Bifurcated Thread Scheduler in a Multithreading Microprocessor

Apparatus and Method for Automatic Low Power Mode Invocation in a Multi-Threaded Processor

Polynomial Arithmetic Operations

Extended Precision Accumulator

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Interrupt Reporting for Single-Bit Memory

Differential Bus with Specified Default Value

System and Method for Coherency in a Split-Level Data Cache System

Variable Delay Line Phase-Locked Loop Circuit

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Microprocessor with Compact Instruction Set Architecture

Microprocessor with Compact Instruction Set Architecture

System and Method for Improving Memory Transfer

System and Method for Automatic Hardware Interrupt Handling

Method and Apparatus for Clearing Hazards Using Jump Instructions

Apparatus for Processing Instructions in a Computing System

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Mechanism for Reduction of Operations Between Interfaces

Translation Lookaside Buffer Shutdown Scheme

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Translation Lookaside Buffer Shutdown Scheme

Variable Delay Line Phase-Locked Loop Circuit

Method of and apparatus using floating point exception signals for controlling several processors

Apparatus and Method for Tracing Instructions with Simplified Instruction State Descriptors

Data Cache Virtual Hint Based Way Prediction

Twice Issued Conditional Move Instruction and Applications Thereof

Apparatus, Method, and Instruction for Initiation of Concurrent Instruction Streams in a Multithreading Microprocessor

Mechanisms for Dynamic Configuration of Virtual Processor Resources

A Cache Way Predictor Scheme

Loop Buffer for Fetch Power Saving in MIPS Cores

Low-Overhead/Power-Saving Processor Synchronization Mechanism, and Applications Thereof

System and Method for Improving Memory Transfer

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Method and Apparatus for Clearing Hazards Using Jump Instructions

A Counter Approach for Distributive Scoreboard Scheduling in an Out-of-Order Microprocessor

Microprocessor with Compact Instruction Set Architecture

Multithreading Microprocessor with Optimized Thread Scheduler for Increasing Pipeline Utilization Efficiency

Bifurcated Thread Scheduler in a Multithreading Microprocessor

Micro Tag Array to Preserve Data Cache Access Power

Apparatus and Method for Automatic Low Power Mode Invocation in a Multi-Threaded Processor

Apparatus and Method for Software Specified Power Management Performance Using Low Power Virtual Threads

System and Method for Automatic Hardware Interrupt Handling

Variable Delay Line Phase-Locked Loop Circuit

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Processor Controlled Interface with Instruction Streaming

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Write request buffering apparatus

Translation Lookaside Buffer Shutdown Scheme

Processor Having a Compare Extension of an Instruction Set Architecture

Mechanism to Extend Computer Memory Protection Schemes

Methods and Apparatus for Improving Fetching and Dispatch of Instructions in Multithreaded Processor

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Debug Mode for a Superscalar RISC Processor

System and Method for Coherency in a Split-Level Data Cache System

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Apparatus for Processing Instructions in a Computing System

Unified Floating Point and Integer Datapath for a RISC Processor

Apparatus for Processing Instructions in a Computing System

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Low-Overhead/Power-Saving Processor Synchronization Mechanism, and Applications Thereof

Method and Apparatus for Improved Computer Load and Store Operations

Queuing System for Processors in Packet Routing Operations

Implementing Atomicity of Memory Operations (as amended from: Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors)

Instruction Fetch and Dispatch in Multithreaded System

Extended Precision Accumulator

Partial Bitwise Permutations

Mechanism for Programmable Modification of Memory Mapping Granularity

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Mechanism for Reduction of Operations Between Interfaces

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Processor, Method and Computer Program Products for Execution of Instructions for Efficient Bit Stream Extractions

MULTI-THREADED PROCESSOR COMPRISING CUSTOMIZABLE BIFURCATED THREAD SCHEDULER FOR AUTOMATIC LOW POWER MODE INVOCATION

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Multithreading Microprocessor with Optimized Thread Scheduler

Apparatus and Method for Software Specified Power Management Performance Using Low Power Virtual Threads

Translation Lookaside Buffer Shutdown Scheme

Write Request Buffering Apparatus

Distributive Scoreboard Scheduling in an Out-of-Order Processor

Twice Issued Conditional Move Instruction, and Applications Thereof (as amended)

Data Cache Virtual Hint Based Way Prediction

Processor Having a Micro Tag Array that Reduces Data Cache Access Power, and Applications Thereof

Preventing Writeback Race in Multiple Core Processors

Low-Overhead/Power-Saving Processor Synchronization Mechanism, and Applications Thereof

Variable Delay Line Phase-Locked Loop Circuit

Method of and Apparatus Using Floating Point Exception Signals for Controlling Several Processors

Two-Level Translation Look-Aside Buffer Using Partial Addresses for Enhanced Speed

Method & Apparatus For Byte Order Switching in a Computer

Variable Page Size Per Entry Translation Look Aside Buffer

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Instructions for Efficient Bit Stream Extraction

Instruction to Enable an Implementation of a Virtual Circular Buffer

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Debug Mode for a Superscalar RISC Processor

System and Method for Coherency in a Split-Level Data Cache System

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Apparatus for Processing Instructions in a Computing System

Unified Floating Point and Integer Datapath for a RISC Processor

Apparatus for Processing Instructions in a Computing System

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

System and Method for Coherency in a Split-Level Data Cache System

Debug Mode for a Superscalar RISC Processor

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Microprocessor Instructions for Efficient Bit Stream Extractions

Microprocessor Instruction to Enable Access of a Virtual Buffer in Circular Fashion

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Support for Multiple Coherence Domains

Variable Register and Immediate Field Encoding in an Instruction Set Architecture

Instruction Prediction Based on Filtering

Prioritized Instruction Scheduling for Multi-Streaming Processors

Register Transfer Unit for Electronic Processor

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Method and Apparatus for Improved Computer Load and Store Operations

Queuing System for Processors in Packet Routing Operations

Implementing Atomicity of Memory Operations (as amended from: Method and Apparatus for Implementing Atomicity of Memory Operations in Dynamic Multi-Streaming Processors)

Instruction Fetch and Dispatch in Multithreaded System

Extended Precision Accumulator

Partial Bitwise Permutations

Mechanism for Programmable Modification of Memory Mapping Granularity

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Mechanism for Reduction of Operations Between Interfaces

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Processor, Method and Computer Program Products for Execution of Instructions for Efficient Bit Stream Extractions

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

Translation Lookaside Buffer Shutdown Scheme

Variable Delay Line Phase-Locked Loop Circuit

Method of and apparatus using floating point exception signals for controlling several processors

Two-Level Translation Look-Aside Buffer Using Partial Addresses for Enhanced Speed

Method & Apparatus For Byte Order Switching in a Computer

Variable Page Size Per Entry Translation Look Aside Buffer

Apparatus for Processing Instructions in a Computing System

Unified Floating Point and Integer Datapath for a RISC Processor

Apparatus for Processing Instructions in a Computing System

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Interrupt Reporting for Single-Bit Memory

Differential Bus with Specified Default Value

Interstream Control and Communications for Multi-Streaming Digital Processors

Processor with Improved Accuracy for Multiply-Add Operations

Load Latency of Zero for Floating Point Load Instructions Using a Load Data Queue

Variable Page Size Translation Lookaside Buffer

Indexing & Multiplexing of Interleaved Cache Memory Arrays

Redundant Mapping Tables

Memory Translation

Address Queue

Polynomial Arithmetic Operations

Apparatus for Processing Instructions in a Computing System

Variable Delay Line Phase-Locked Loop Circuit

Method of and apparatus using floating point exception signals for controlling several processors

Method and Apparatus for Clearing Hazards Using Jump Instructions

Two-Level Translation Look-Aside Buffer Using Partial Addresses for Enhanced Speed

Method & Apparatus For Byte Order Switching in a Computer

Initiation of Concurrent Instructions Streams

Mechanisms for Dynamic Configuration of Virtual Processor Resources

Suspension and Deallocation of Computational Threads of Execution in a Processor

Variable Page Size Per Entry Translation Look Aside Buffer

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Instruction to Enable an Implementation of a Virtual Circular Buffer

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Bifurcated Thread Scheduler in a Multithreading Microprocessor

Mechanism and Method for Integer Divide Involving Pre-Alignment of the Divisor Relative to the Dividend

Debug Mode for a Superscalar RISC Processor

System and Method for Coherency in a Split-Level Data Cache System

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Extended Precision Accumulator

Partial Bitwise Permutations

Mechanism for Programmable Modification of Memory Mapping Granularity

Mechanism for Reduction of Operations Between Interfaces

Integrated Mechanism for Suspension and Deallocation of Computational Threads of Execution in a Processor

Processor, Method and Computer Program Products for Execution of Instructions for Efficient Bit Stream Extractions

MULTI-THREADED PROCESSOR COMPRISING CUSTOMIZABLE BIFURCATED THREAD SCHEDULER FOR AUTOMATIC LOW POWER MODE INVOCATION

Dual Byte Order Computer Architecture A Functional Unit for Handling Data Sets with Different Byte Orders

CPU Chip Having Cache Tag Comparator & Address Translation Unit on Chip & Connected to Off-Chip Cache & Main Memories

Write Request Buffering Apparatus

Translation Lookaside Buffer Shutdown Scheme

Processor Controlled Interface with Instruction Streaming

System and Method for Booting Computer for Operation in Either of Two Byte-Order Modes

Method and Apparatus for Binding Shadow Registers to Vectored Interrupts

Variable Delay Line Phase-Locked Loop Circuit

Method of and apparatus using floating point exception signals for controlling several processors

Two-Level Translation Look-Aside Buffer Using Partial Addresses for Enhanced Speed

Superscalar Microprocessor Instruction Pipeline Including Dispatching and Kill Control

Method & Apparatus For Byte Order Switching in a Computer

Variable Page Size Per Entry Translation Look Aside Buffer

Backward Compatible Computer Architecture with Extended Wordsize and Address Space

Backward Compatible Computer Architecture with Extended Wordsize and Address Space