IP3 2025 – Semic Fabrication 4 (Lot 16768)

This lot is generally related to a negative transconductance device with multiple threshold voltages that uses a heterojunction structure to support multi-state logic in low-power electronics, enable compact and energy-efficient analog or mixed-signal circuits, and provide greater flexibility in designing neuromorphic or adaptive circuits. The disclosed negative transconductance device consists of one transistor with a P-type channel, one transistor with an N-type channel, and the third transistor with an ambipolar channel. Also disclosed is that the P-type transistor’s drain is connected to the ambipolar transistor’s source, and the ambipolar transistor’s drain is connected to the N-type transistor’s source. Further disclosed is that all three gate electrodes share the same input voltage, enabling a coordinated current response with unique electronic behavior. The technology may be implemented in oscillators, amplifiers, adaptive computing hardware, next-generation semiconductor devices, etc.